1. Field of the Invention
This invention relates to a semiconductor device and more particularly to a semiconductor device of a complementary IC (integrated circuit).
2. Description of the Prior Art
FIG. 1 is a schematic sectional view of a conventional semiconductor device of a complementary IC. Such a complementary IC device is shown, e.g., in page 89 of PRINCIPLES OF CMOS VLSI DESIGN edited by N. H. E. Weste and K. Eshraghian and published 1985 by Addison-Wesley Publishing Co. In FIG. 1, an n-semiconductor substrate 1 includes a p-well 2. A contact p-region 3 is formed in the surface region of the p-well 2 and connected to a grounded line 9 through a contact hole opened in an insulator layer 15. Similarly, a contact n-region 4 is formed in the surface region of the n-substrate 1 and connected to a voltage source line 10. A source 5a, a drain 5b and a gate electrode 6 constitute an n-channel MOS (metal oxide semiconductor) transistor on the p-well 2. The source 5a is connected to the grounded line 9, while the drain 5b is connected to an output line 11. Similarly, a source 7a, a drain 7b and a gate electrode 8 constitute a p-channel MOS transistor on the n-substrate 1. The source 7a is connected to the voltage source line 10, and the drain 7b is connected to the output line 11.
In the device of FIG. 1, potential of the n-substrate 1 is stabilized by means of the n-contact 4 and voltage source line 10. Similarly, potential of the n-well 2 is stabilized by means of the p-contact 3 and grounded line 9. Therefore, a parasitic p-n-p-n thyristor constituted of the p-source 7a, n-substrate 1, p-well 2 and n-source 5a is hardly activated, so that the latch-up phenomenon may be prevented. The latch-up phenomenon is described in detail, e.g., in the Japanese Patent Laying-Open Gazette No. 58-130557 (1983) or the corresponding U.S. Pat. Application Ser. No. 338778 filed 1/11/82 and now abandoned.
In the conventional complementary IC device of FIG. 1, however, if a noise potential such as a surge is accidentally introduced in the output line 11, the surge will reach the source 5a or 7a depending on the state of the corresponding MOS transistors and then spread through the grounded line 9 or voltage source line 10 into the p-well 2 or n-substrate 1. For example, when the output line 11 outputs a high level, the p-channel MOS transistor on the n-substrate is in an on-state. In this situation, the surge reaches the source 7a and enters the n-substrate 1 through the voltage source line 10 and n-contact 4. As a result, the potential of the n-substrate becomes unstable. This unstable potential may act as a trigger of activating the above described parasitic thyristor and then the latch-up phenomenon tends to be caused.